1. Field of the Invention
The present invention relates to a capacitor device and a semiconductor device having the same and a capacitor device manufacturing method and, more particularly, a capacitor device capable of being applied as a decoupling capacitor that is arranged on the circuit board, on which the high speed LSI is mounted, to not only stabilize a power supply voltage but also reduce a high frequency noise, and a semiconductor device having the same and a capacitor device manufacturing method.
2. Description of the Related Art
In recent years, in the digital LSIs including the microprocessor, a reduction in the power supply voltage is carried forward on account of an increase in the processing speed and a reduction in the power consumption. In such digital LSIs, the power supply voltage of the LSI is liable to become unstable when the impedance of the LSI is abruptly varied, and so forth. Also, in the high speed digital LSI, a stable operation in a higher frequency (GHz) range is required and thus it is necessary to prevent a malfunction of the LSI due to the high frequency noise.
Therefore, for the purpose of stabilizing the power supply voltage and reducing the high frequency noise, a decoupling capacitor is arranged between a power supply line and a ground line of the LSI.
In the circuit boards having the conventional decoupling capacitor, there is such a circuit board (front side package type) that the LSI chip and the capacitor parts are packaged on one surface (front side) of the circuit board and connection terminals are provided on other surface (rear side) of the circuit board. In the front side package type, since leads must be provided between the LSI chip and the capacitor parts, a relatively large inductance is present between the leads. As a result, an effect of the decoupling capacitor is lessened.
Therefore, as shown in FIG. 1, in order to reduce a wiring length between the LSI chip and the decoupling capacitor, there is such a circuit board (back side package type) that an LSI chip 104 is packaged on one surface (front side) of a circuit board 100, on both surfaces of which mutually-connected wiring patterns 102 are provided, and capacitor parts 106 are packaged on the other surface (back side).
Also, in order to make the multi-layered wiring structure simple, there is such a circuit board that the capacitor parts are embedded in the insulating layer of the circuit board (for example, Patent Literature 1 (Patent Application Publication (KOKAI) 2002-261449)).
In addition, in Patent Literature 2 (Patent Application Publication (KOKAI) 2000-243873), there is set forth such a circuit board that the laminated ceramic capacitor is packaged in the recess portion provided in the core board in a state that the capacitor is buried in the filling resin and the resin insulating layer and the wiring layers are provided thereon and thereunder.
However, in the back side package type shown in FIG. 1, a wiring length between the LSI chip and the decoupling capacitor can be shortened rather than the front side package type, nevertheless areas on the back side, in which a connection terminal 108 is arranged respectively, are restricted because the capacitor parts 106 are packaged on the back side of the circuit board 100. In addition, as indicated by a broken line in FIG. 1, since the wirings must be provided horizontally from the capacitor parts 106 to the connection terminals 108 on the back side of the circuit board 100, there is a limit to a reduction in the parasitic inductance and thus it is assumed that an effect of the decoupling capacitor is lessened. Further, the problem that the back side package type cannot easily respond to an increase of the wiring density still remains.
Also, in Patent Literature 1, the technology to minimize the parasitic inductance by reducing the wiring length between the LSI chip and the decoupling capacitor is not satisfactorily considered. In addition, in Patent Literature 2, an effect of reducing the inductance of the wirings connected to the laminated ceramic capacitor on and under which the connection pads are provided can be attained, nevertheless the core board must be processed in a complicated manner. Therefore, the manufacturing steps become complicated and also there is a limit to a reduction in the parasitic inductance because the wirings must be formed to pass through the core board.